Configuring COIDE for NUCLEO-F401RE

I managed to configure the free IDE from Coocox, COIDE, for programing my  ST NUCLEO-F401RE board with ARM-GCC.

The current version of COIDE (1.7.7) does not support the microcontroller of this board (STM32F401RE). However it support the STM32F401RC. The only difference between them is the amount of RAM and FLASH. Therefore, I created a project in COIDE for STM32F401RC and changed it for the STM32F401RE. I present here a description of what you have to do in order to configure the project correctly.

1. COIDE setup

1.1. Linker Memory Areas 

In COIDE project configuration, Link tab change the IROM1 size to 0x00080000 (512kB) and IRAM1 size to 0x00018000 (96kB). The start address for IROM1 is 0x08000000 and for IRAM1 is 0x20000000.

1.2. Programming Algorithm

In project configuration, Download tab, in Programming Algorithm area change the file path. Instead of pointing to file STM32F4xx_256.elf the path should point to file STM32F4xx_512.elf that is located in the same directory of the original file.

1.3. Clock

The default clock configuration for any STM32F4 device in COIDE assumes that you have a 25MHz crystal oscillator and a 168MHz device. This is not the case. Therefore, it is necessary some modifications in the code. My nucleo board can use an 8MHz external clock derived from STLINK debugger. This can change according to the version of your board. Check the Nucleo User Manual.

Change the system_stm32fxx.c:

At the beginning of the file adjust the values of the PLL configuration.

/************************* PLL Parameters *************************************/
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M      8
#define PLL_N      336

/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P      4

/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
#define PLL_Q      7

/******************************************************************************/

Update the SetSysClock function, in the same file. At the beginning, add  RCC->CR |= ((uint32_t)RCC_CR_HSEBYP); before RCC->CR |= ((uint32_t)RCC_CR_HSEON); to bypass the clock oscillator and use the external input.

  /* Enable HSE bypass */
RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
RCC->CR |= ((uint32_t)RCC_CR_HSEON);

Correct the AHB, APB1 and APB2 prescallers:

/* HCLK = SYSCLK / 1 (AHB PRESCALLER) */
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK / 1 (APB2 PRESCALLER) */
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK / 2 (APB1 PRESCALLER) */
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;

You can also enable  the FLASH prefetch with 2 wait states that is the minimum possible for a 84MHz clock and 3.3V supply. Update this if you use a different clock frequency.

/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;

Change the stm32f4xx.h

Finally you have to change the HSE_VALUE definition in stm32f4xx.h to match your crystal or external clock frequency (in this case 8MHz). Change it to:

#if !defined  (HSE_VALUE) 
  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */

That's it. Remember to call SystemInit(); and SystemCoreClockUpdate(); at the begining of your main function.

2. Example project

Im my github account you will find an example project to download.
Check it out at:
https://github.com/miguelmoreto/NucleoF401-COIDE-blink

This example is based on the post http://developer.mbed.org/forum/platform-34-ST-Nucleo-F401RE-community/topic/4855/

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